Microelectronics Development Methodology
ASICs (Application Specific Integrated Circuits) and FPGA (Field Programmable Gate Arrays) are commonly used on-board spacecraft in large quantities. On top of the normal constraints and tools for ASIC and FPGA developments, reliability and radiation tolerance are of particular concern in space applications, and therefore, specific design methods and tools and standards are required. Part of our work aims also at investigating methodologies from commercial chip development and COTS tools used therein
ECSS ASIC, FPGA and IP Core engineering and product assurance standards
The ECSS standards for ASIC, FPGA and IP Core engineering ECSS-E-ST-20-40C and product assurance ECSS-Q-ST-60-03C were published on October 11th, 2023.
ECSS-E-ST-20-40C defines the generic DEVICE (i.e. an ASIC, or an FPGA or an IP Core) development flow and provides a comprehensive set of engineering requirements covering all phases of the development and the expected outputs that shall be reviewed at the end of each phase, as depicted in this figure:
ECSS-Q-ST-60-03C complements ECSS-E-ST-20-40C with product assurance requirements.
The following files can be downloaded as additional resources to help understand and apply these standards:
- Introduction to the new ECSS standards for ASIC, FPGA and IP Cores, for people NOT familiar with old ECSS-Q-ST-60-02C – pdf slides – webinar video recording (Jan 18th, 2024) (2.5h)
- Introduction to ECSS standards for ASIC, FPGA and IP Cores, for people familiar with old ECSS-Q-ST-60-02C – pdf slides – webinar video record (Jan 23rd, 2024) (2.5h)
- Excel table to assist with tailoring of ECSS-E-ST-20-40C requirements
- Excel table to assist with tailoring of ECSS-Q-ST-60-03C requirements
- Excel table with all expected outputs (both E and Q) to assist with customer-supplier agreement for contractual deliverables
- Comparison of the new (ECSS-E-ST-20-40C) and old (ECSS-Q-ST-60-02C) development flows
“ECSS qualification” of any newly developed DEVICE is subject to the successful closure of all phase reviews as so declared by the customer engineering responsible person (usually an ESA microelectronics expert supervising the DEVICE development), assisted by a product assurance responsible person for cases of critical DEVICE developments to be flown in ESA projects.
For already existing DEVICEs for which there is not enough evidence that the DEVICE was developed according to ECSS engineering and product assurance standards, further evaluation and qualification tests following ESCC specifications can be requested by ESA projects.
Note that all ECSS standards can be downloaded (after registration) from use of those IP Cores, tailoring according to DEVICE criticality and DEVICE type, new definitions and coherent use of the same key terminology (also used in other standards), development flow flexibility to accommodate parallel or iterative flows, additional and more clear requirements, including more examples, separation between engineering and more explicit product assurance requirements, were a few of the improvement goals that the ECSS WG worked on. The new standards underwent a lengthier than usual Public Review of 6 months, where more than 315 request for changes to the final draft were submitted from industry and institutions. The ECSS WG processed and implemented carefully most of thoth 2023.se additional ideas which further helped to improve the final version of the standards published on October 11th 2023.
The previous ECSS-Q-ST-60-02C ASIC/FPGA Development standard was developed between 2000 and 2007, when its first edition was published. It was the result of a joint initiative between ESA, TESAT and the European Cooperation for Space Standardisation (ECSS), with participation of reviewers in European industry. The standard is made available at this site as legacy reference.
Prior to ECSS-Q-ST-60-02C, these two other documents were used for ESA technology development contracts to minimise development risks and avoid "unpleasant surprises" late in the development: ASIC Design and Manufacturing Requirements (WDS/PS/700 1994) and ASIC Design and Assurance Requirements (QC/172/RdM 1992)
ECSS-E-HB-20-40A "Engineering techniques for radiation effects mitigation in ASICs and FPGAs handbook"
This ECSS Handbook was published on September 1st, 2016 under the name ECSS-Q-HB-60-02A “Techniques for radiation effects mitigation in ASICs and FPGAs handbook” and was renamed to ECSS-E-HB-20-40A “Engineering techniques for radiation effects mitigation in ASICs and FPGAs handbook” on October 11th, 2023, coinciding with the publication of the new ECSS standards for engineering and product assurance of ASIC, FPGA and IP Core: ECSS-E-ST-20-40C and ECSS-Q-ST-60-03C respectively. ECSS handbooks and standards can be downloaded (after registration) from http://www.ecss.nl/
The ECSS-E-HB-20-40A handbook provides a compilation of more than 75 different techniques that can be used to mitigate the various adverse effects of radiation in integrated circuits (ICs), with special attention to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) to be used in space. These large number of mitigation techniques have been classified in 10 groups and 4 levels:
The target users of this handbook are developers and users of ICs to be used in a radiation environment. Following a bottom-up order, the techniques are presented according to the different stages of an IC development flow where they can be applied. Therefore, users of this handbook can be IC engineers involved in the selection, use or development of IC manufacturing processes, IC layouts and ASIC standard cell libraries, analogue and digital circuit designs, FPGAs, embedded memories, embedded software and the immediate electronic system (printed circuit board) containing the IC that can experience radiation effects.
In addition, this handbook contains a short overview of the space radiation environment and its effects in semiconductor devices, a section explaining 15 different ways to validate the good implementation and effectiveness of the mitigation techniques, and a special section providing some general guidelines to help with the selection of the most adequate combination of mitigation techniques.
As in all ECSS handbooks, the information given in this handbook is provided as guidelines, and not as requirements. This handbook includes more than 340 bibliographic references.
Complementing this Handbook, the following two documents are available for download at this site:
ECSS-E-HB-20-40A Annex (informative) Vendor- or institute-ready ASIC and FPGA technology solutions that include mitigation against radiation effects or that can help to introduce mitigation and/or to validate it
ECSS-E-HB-20-40A Acknowledgements thanking the many experts, companies and institutions who contributed to write this handbook.
ESA IP Core Technical Requirements
The objective of this document is to describe the technical requirements and the minimum set of deliverables expected, in order to allow a design to be reused as an “Intellectual Property Core”, or IP core. The main subject of this document is the “soft IP cores”, i.e. IP cores that are delivered to the Agency as synthesizable RTL HDL code: ESA IP Core Technical Requirements. This document complements and is in addition to the requirements for IP Core developments covered by ASIC, FPGA and IP Core Engineering
FT-UNSHADES
FT-UNSHADES is a test system dedicated to the study of Fault Tolerant Circuits and the measurement of the robustness of an ASIC netlist against soft errors. It is based on a proprietary method for inserting controlled modifications into the current state of the emulator device (Xilinx Virtex-II, XC2V4000, XC2V6000, XC2V8000) during execution time. Using this board and software, fault tolerance detailed analysis can be produced before IC fabrication. The project was designed and engineered by a team of researchers from the Electronics Engineering Department of the University of Seville under an ESA contract.
The SEUs Simulation Tool (SST)
The SEUs Simulation Tool (SST) is a set of Perl and TCL scripts which allow the injection of SEU-like faults into HDL and netlist simulations.
The Design Under Test (DUT) is analyzed, and a list of nodes is provided to the user. After user selection of a fault scenario, appropriate TCL "force" commands are generated for the simulator (ModelSim), which will then upset selected nodes of the design at the selected time during simulation. (pdf available)
- Author : Daniel Gonzalez Gutierrez
The tool is provided for free download under GPL licence. However, if you download and use this tool, please inform us by sending a mail to IpCoreRequest[at]esa.int and provide feedback/bugfixes to this same address. (zip file available)
Feel free to also visit the SST page at University Antonio de Nebrija, containing release 2.0 (November 2006). (see "Related links").
