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Technologies for Space
Microelectronics Technologies for Space
The use of reprogrammable FPGAs in space
ESA IP Cores
About ESA IP Cores
ESA HDL IP Cores Portfolio Overview
IP Cores Library
AHBR
AUIP
CAN
CCIPC
CUC-CTM
EDAC
IP1553
IPMON
LEON2-FT
PDEC
PTCD
PTME
RT53EUR
SHyLoC IP Core
SpW-AMBA
SpWb
SpW-RMAP-Astrium
SpW-RMAP-Dundee
SpWTDP
SpaceFibre Port IP Core
SCCC IP Core
SystemC IP-Cores
Discontinued IP-Cores
VCA, VCM, TCE - HDL
OBDH
EVI32
WIC
Usage Statistics
Licensing
Events
IP Cores Workshop 2005
ESA IP-Cores Day - 2nd edition
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Development Methodology
Microelectronics Development Methodology
VHDL
VDHL models for board-level simulation
System-On-Chip (SOC)
System-On-Chip (SOC) Development
IP-Cores for SOC Developments in Space Applications
SOC Development Activities
The AMBA Bus System
Documents Related to SOC and IP-Core-Based Design
ASIC Developments History
Ongoing ASIC developments
Completed ASIC developments (recent)
Completed ASIC developments (older)
System Level Modeling
Electronic System-Level Design Methodology
System-Level Modeling in SystemC
SystemC IP-Cores Library
LEON2/3 Integer Unit - SystemC
SpaceWire-b CODEC - SystemC
SoCROCKET Virtual Platform - SystemC
Virtual Platform Technology
Mixed Signal ASIC Technology
Analogue and Mixed-Signal IPs for Space
IMEC/UMC DARE180
XFAB 180 (XH018)
ATMX150RHA
TSMC 90nm Low-Power 1.2V
IHP SGB25RH
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