CAN
The design of the Controller Area Network (CAN) VHDL IP core started as a prototype activity with the intention to understand the internal of a CAN (Controller Area Network) controller and not to develop the full controller.
It was then gradually taken to the present level in a low level priority activity. The HurriCANe has now gone through 4 major versions with a major improvement in the release 3.
The latest release includes the CAN B features not available in the previous releases.
Overview
The HurriCANe is a VHDL core comprising the following elements:* CAN controller core,
* AMBA APB wrapper (to integrate the CAN core into a system-on-chip),
* testbenches,
* synthesis scripts and reports,
* documentation.
The HurriCANe Design Hierarchy is illustrated in the following diagram (click on thumbnail to enlarge).
The following block diagram illustrates the internal structure of the CAN core in a bit more detail (click on thumbnail to enlarge).
Area/Speed Results
CAN 5.2.4 on ACTEL A54SX72A
- Combinational cells : 1217 of 4024 (30%)
- Sequential cells : 530 of 2012 (26%)
- Total cells : 1747 of 6036 (31%)
- Clock buffers : 2
- Max clock frequency : 10.4 Mhz
Developers and contributors
Luca Stagnaro (ESA), Massimigliano Bracco (ESA) - CAN v.4.6 (1999)
Egidio Pescari (Aurelia Microelettronica S.p.A.) - CAN v.5.0 (2001)
Francisco Tortosa Lopez (ESA) - CAN v.5.1 (2005)
Fabrizio Bertuccelli (Aurelia Microelettronica S.p.A.) - CAN v.5.2.4 (2008)
Current Release
Version 5.2.4, 26-May-2008
An encrypted Modelsim (6.3d) simulation model is available for evaluation.
For a history of bug reports and fixes, modifications, upgrades, etc, please refer to the CAN IP Core Release Notes.
Special licensing restrictions
None. In case the IP-Core is used outside of an ESA activity/project, a license has to be obtained from Bosch for the use of the patents on the CAN Protocol.
