ESA Contracts Final Reports
The following is a list of Final Reports and Executive Summaries of ESA contracts led by the Microelectronics section. These documents are posted publically, with the consent of the ESA contractors and never disclosing company confidential information, in order to facilitate the dissemination of the technology achievements and progress accomplished by our space industry. The results of these contracts have also been presented in Microelectronics Presentation Days and other international workshops and conferences.
Multi-Core architectures - Cache structure optimisation for better RT performance
The main goal of this activity is to understand the philosophy of the Performance- Monitoring Counter (PMC) implemented in current multi-core processors and suggest improvements over the performance monitoring infrastructure currently implemented in the NGMP processor
Development of new SystemC IP models and OCP-IP sockets
The main aspect of this project was the development of new SystemC IP-core models, extension of existing ones with new functionalities, and integration into the existing SoCRocket simulation infrastructure
- Prime contractor: Terma (DE)
- Date: June 2014 (pdf)
Multi-threaded processor for space applications
The objective of this work was to investigate the benefit of multi-threaded processors in space. This includes the benefit to generic applications as well as to two specific areas which are critical for space missions, i.e. real-time tasks, where multi-threading should be able to provide tighter bounds for the worst-case execution time for real-time tasks; and reliability, where multi-threading can provide more efficient support for redundant execution.
A software emulator of the proposed multi-threaded processor was used to evaluate these applications and to demonstrate advantages over non-threaded procssors.
- Prime contractor: University of Amsterdam (NL)
- Date: April 2013 (pdf)
Manufacture and Validation of LEON4FT Multiprocessor Prototype Device
implementation and validation on a deep sub-micron ASIC technology of the NGMP Processor Architecture.
- Prime contractor: Aeroflex Gaisler (S)
- Date: May 2013 (pdf)
SoCRocket: HW/SW Co-Simulation
The goal of this study is the development of a design flow (DF) for Virtual Platform (VP) implementation and validation. The study includes the modeling and the verification of Transaction Level Modeling (TLM) components and the design of a proof-of-concept VP.
- Prime contractor: University of Braunschweig (D)
- Date: Dec 2012 (pdf)
Broadband Low Power DAC
The main objective of this project is to develop, build, and test a DAC prototype for the next generation of digital telecommunication payloads.
- Prime contractor: Kayser-Threde GmH (D)
- Date: Oct 2012 (pdf)
AT697 F
Development of the AT697F flight models based on the LEON2-FT VHDL model.
- Prime contractor: Atmel (F)
- Date: Aug 2012 (pdf)
Spacecraft Controller On a Chip (SCOC3)
Spacecraft Controller On-a Chip Design, Manufacturing and Validation (to be complemented with SEE test results).
- Prime contractor: Astrium Elancourt
- Date: July 2012 (pdf)
10bit ADC
Development of a 10 bit ADC
- Prime contractor: E2V (F)
- Date: Dec 2011 (pdf)
DELTA
Development of a SystemC model of ECSS-E-ST-50-12C, SpaceWire-CODEC
- Prime contractor: Qualtek (BE)
- Date: Nov 2010 (pdf)
ACN - HIFAS
Highly Integrated Full-custom Autocorrelation Spectrometer.
- Prime contractor: Omnisys
- Date: December 2009 (pdf)
80S32 Validation
Validation of the 80S32 MicrocontrollerIntegrated Systems Development
- Prime contractor: ISD
- Date: July 2009 (pdf)
FLIPPER
A fault injection system to investigate the SEU effects on designs implemented in SRAM based FPGA.
- Prime contractor: University of Milan (IASF)
- Date: Jan 2009 (pdf)
FT-Unshades Experience
FT-Unshades SEU Emulations to the LEON2 processor, comparing the unprotected version, the LEON2-FT (fault-tolerance in source code) and a version protected by Xilinx TMR tool.
- Prime contractor: University of Seville
- Date: Feb 2006 (pdf)
Flexwave-II
Development of a Wavelet Image Compression IP and Implementation on an FPGA Demonstrator board.
- Prime contractor: IMEC, Belgium
- Date: August 2005 (pdf)
IRIS3
Development of a Rad-Hard CMOS Image Sensor and an Integrated Microcamera.
- Prime contractor: IMEC, Belgium
- Date: August 2005 (pdf)
HSDEM
A high-speed digital modulator has been developed under the ARTES 3 program. An Engineering Qualification Model (EQM) of the modulator was successfully built and tested.
- Prime contractor: ComDev, Canada
- Date: July 2005
FT-UNSHADES
SEU Fault-Tolerance Validation of ASIC designs by fault injection using an SRAM based FPGA.
- Prime contractor: University of Seville
- Date: May 2005
ACS
A full-custom Autocorrelation Spectrometer Chipset, comprising a bipolar 3-level quantiser, a 128-channel and a 1024-channel correlator chip, both in CMOS.
- Prime contractor: Omnisys, Sweden
- Date: March 2005 (pdf)
DARE
Design Against Radiation Effects - Analysis and validation of the possibility to use a commercial standard technology of which radiation withstanding could be improved by design, at library level.
- Prime contractor: IMEC, Alcatel Space
- Date: November 2004 (pdf)
SCOC
Spacecraft Controller On-a Chip - Definition, development and demonstration on FPGA of a complex System-On-Chip device (other documents/presentations).
- Prime contractor: EADS-Astrium Velizy
- Date: June 2004 (pdf)
LEONUMC
Development and SEU testing of the LEON2FT processor in commercial UMC 0.18um technology.
- Prime contractor: IMEC, ESA internal, Gaisler Research
- Date: May 2004
BroadCast
A flexible modem platform serving WCDMA- like and related communications needs has been designed, implemented and thoroughly tested in the field.
- Prime contractor: Sirius/Agilent (B)
- Date: May 2003 (pdf)
ChipSat
A System-on-a-Chip for Small Satellite Data Processing and Control.
- Prime contractor: Surrey Space Centre (UK)
- Date: March 2003 (pdf)
T@MPO
A High Throughput Turbo Codec at Minimum Power.
- Prime contractor: IMEC (B)
- Date: February 2003 (pdf)
GNSS Front-End
Feasibility Study for a low risk, low cost, low power fully integrated front end in deep-sub-micron CMOS.
- Prime contractor: ChipIdea (Portugal)
- Date: Jan. 2003 (pdf)
SRAM based FPGA
The Use of SRAM Based FPGA in Space. Several documents are the output of this study contract.
- Prime contractor: Gaisler Research (S)
- Date: 2002
MSREM
Miniaturised Standard Radiation Environment Monitor.
- Prime contractor: Contraves (CH)
- Date: August 2002 (pdf)
FFASIC
Fixed Function ASICs: Radiation-Hardened by design on deep-submicron commercial technology.
- Prime contractor: IMEC (B)
- Date: April 2002 (pdf)
80S32
Microcontroller 80S32 for On-Board Data Handling.
- Prime contractor: ADV/Transwitch (F)
- Date: July 2001 (pdf)
Circumventing Radiation Effects by Logic Design
One of the objectives of this R&D is to write a design manual for helping the designers to take into account the Single Event Upset (SEU) and Single Event Latchup (SEL) aspects. This manual first describes the space origin of the ionising particles leading to Single Event Upsets in electronic systems, and then gives some explanations about the physical aspects of Single Event Effects (SEE). The manual also serves as a cookbook, giving “design recipes” for chip protections against SEU and SEL. These recipes can be either at function level or at cell level for ASIC design.
